Overview:
| CPU | 16BP |
| Data | 16 bits |
| Memory | 24 bits? |
| Registers | ? |
| Architecture | Von Neumann |
| Technology | Verlog on FPGA |
| Status | Not really started |
| Successor | None |
| Time period | December? 2016 - ? |
16BP would be quite a bit fancier than 8BP3. The plans were for it to be pipelined and use branch prediction. In addition, there would be hardware support for paging and virtual memory. Maybe even supervisor and user modes. We may never know, since it seems Adelie may be delivered in a 16-bit version as well.
Files:
For all of this talk about how little I worked on the CPU, there sure is a lot of information. Hmm... Some of these ideas look good. Dare I restart it?
16BP Verilog sources (zip)
Seriously? Microcode states? I must have been a bit farther in the design process than I remember.
Microcode states (txt)
Just testing assembly. No HEX files.
Test programs (zip)
16BP Instruction set v1 (xlsx)
16BP Instruction set v2 (xlsx)
Are you sure you didn't use Microsoft Paint?
16BP Block Diagram (png)
Notes (txt)
Development Checklist (txt)
SPCx is a reference to the potential Small Peripheral Computer project.
LPC refers to linear predictive coding
Wishlist (txt)
Boy, is this tempting.
Updated 6/29/2019