/*
There are 53 official instructions.
fr, ivr, sp, and pc are memory mapped.
There are eight 16-bit address registers.
There are 64 data registers of which eight are address registers.
There is one 16-bit interrupt vector register (ivr).
The instruction pipeline is 4 words deep.
Queue size is 6 instructions deep.
Each instruction pipeline is able to convert the current instruction to a nop.

Memory map:
		 ________________
0x0000	|                |	Reset
		|________________|
0x0002	|                |	Exception
		|________________|
0x0004	|                |	Free memory
		|                |
		|                |
		|                |
		|                |
	   ~~~~~~~~~~~~~~~~~~~~
		|                |
		|                |
		|                |
		|                |
		|________________|
0xFFBC	|________________|	Flag Register
0xFFBD	|________________|	Program Counter
0xFFBE	|________________|	Stack Pointer
0xFFBF	|________________|	Interrupt Vector
0xFFC0	|                |	General purpose registers
		~~~~~~~~~~~~~~~~~~
		|________________|
0xFFF8	|                |	Address registers
		~~~~~~~~~~~~~~~~~~
0xFFFF	|________________|

address		16
mask		16
areg		2
reg			6
data		16
addr8		8
shift		4
cc			9
rcc			8
*/

.PROCESSOR 16BP_2
.INCLUDE "16BP_2.uhpl"

.EQU address 0x0000
.EQU mask 0x0000
.EQU data 0x0000
.EQU addr8 0x00
.EQU shift 0x0
.EQU rcc 0x00
.EQU cc 0x000

.DEF areg a0
.DEF reg r0

//Instruction set:
NOP					;Also known as a "bubble"
JMP address
RET
RETI
PSHF
POPF
CLRF mask
SETF mask
CALL address
IJMP areg
ICAL areg
LDI reg data
INT reg				;Does not set I bit in flags.
NOT reg
NEG reg
INC reg
DEC reg
PUSH reg
POP reg
ADDI reg data
ADCI reg data
SUBI reg data
SBCI reg data
ANDI reg data
ORI reg data
CMPI reg data
XORI reg data
TEST reg
LDD reg address
STD address reg
RJMP addr8			;RJMP uses an 8-bit address.
LD reg areg
ST areg reg
ASR reg shift
ASL reg shift
ROR reg shift
ROL reg shift
SHR reg shift
SHL reg shift
XOR reg reg
MOV reg reg
CMP reg reg
ADD reg reg
ADC reg reg
SUB reg reg
SBC reg reg
AND reg reg
OR reg reg
MULT reg reg		;The product of the two registers is stored in the first two data registers. Little Endian.
DIV reg reg			;The quotient is stored in data register 1, and the remainder is stored in data register 0.
IBR.rcc areg
BR.cc address
RBR.cc address		;RBR. uses a 16-bit address