//16BP-2 state table.

nop		mem[pc]->cu, pc++
		
jmp		mem[pc]->cu, pc++
		mem[pc]->pc, pc++
		
ret		mem[pc]->cu, pc++
		mem[sp]->pc, sp++
		
reti	mem[pc]->cu, pc++
		mem[sp]->pc, sp++, 0->I
		
pshf	mem[pc]->cu, pc++
		fr->mem[sp], sp--
		
popf	mem[pc]->cu, pc++
		mem[sp]->fr, sp++
		
clrf	mem[pc]->cu, pc++
		fr & ~mem[pc]->fr, pc++
		
setf	mem[pc]->cu, pc++
		fr | mem[pc]->fr, pc++
		
call	mem[pc]->cu, pc++
		pc + 1->mem[sp], sp++, halt pipeline
		mem[pc]->pc
		
ijmp	mem[pc]->cu, pc++
		reg[ar# + 56]->pc
		
ical	mem[pc]->cu, pc++
		pc + 1->mem[sp], sp++, halt pipeline
		reg[ar# + 56]->pc
		
ldi		mem[pc]->cu, pc++
		mem[pc]->reg[dr#], pc++
		
int		mem[pc]->cu, pc++
		pc->mem[sp], sp++, halt pipeline?
		iv->pc (private bus?)
		
not		mem[pc]->cu, pc++
		nop
		~reg[dr#]->reg[dr#], prefetch
		
neg		mem[pc]->cu, pc++
		nop
		-reg[dr#]->reg[dr#], prefetch
		
inc		mem[pc]->cu, pc++
		nop
		reg[dr#] + 1->reg[dr#], prefetch
		
dec		mem[pc]->cu, pc++
		nop
		reg[dr#] - 1->reg[dr#], prefetch
		
push	mem[pc]->cu, pc++
		reg[dr#]->mem[sp], sp--
		
pop		mem[pc]->cu, pc++
		mem[sp]->reg[dr#], sp++
		
addi	mem[pc]->cu, pc++
		mem[pc]->alur
		reg[dr#] + alur->reg[dr]

		//reg[dr#] + mem[pc]->reg[dr#], pc++
		
adci	mem[pc]->cu, pc++
		reg[dr#] + mem[pc] + C->reg[dr#], pc++
		
subi	mem[pc]->cu, pc++
		reg[dr#] - mem[pc]->reg[dr#], pc++
		
sbci	mem[pc]->cu, pc++
		reg[dr#] - mem[pc] - C->reg[dr#], pc++
		
andi	mem[pc]->cu, pc++
		reg[dr#] & mem[pc]->reg[dr#], pc++
		
ori		mem[pc]->cu, pc++
		reg[dr#] | mem[pc]->reg[dr#], pc++
		
cmpi	mem[pc]->cu, pc++
		reg[dr#] - mem[pc] (Set flags accordingly), pc++
		
xori	mem[pc]->cu, pc++
		reg[dr#] ^ mem[pc]->reg[#dr], pc++
		
test	mem[pc]->cu, pc++
		reg[dr#] - 0 (Set flags accordingly), prefetch
		
ldd 	mem[pc]->cu, pc++
		mem[pc]->reg[dr#], pc++
		
std		mem[pc]->cu, pc++
		reg[dr#]->mem[pc], pc++
		
rjmp	mem[pc]->cu, pc++
		pc + 8b_addr->pc
		
ld		mem[pc]->cu, pc++
		mem[reg[ar# + 56]]->reg[dr#]
		
st		mem[pc]->cu, pc++
		reg[dr#]->mem[reg[ar# + 56]]
		
asr		mem[pc]->cu, pc++
		(reg[dr#]>>shft) | (S<<15)->reg[dr#], prefetch
		
asl		mem[pc]->cu, pc++
		reg[dr#]<<shft->reg[dr#], prefetch
		
ror		mem[pc]->cu, pc++
		(reg[dr#]>>shft) | (reg[dr#][0]<<15)->reg[dr#], prefetch
		
rol		mem[pc]->cu, pc++
		(reg[dr#]<<shft) | reg[dr#][15]->>reg[dr#], prefetch
		
xor		mem[pc]->cu, pc++
		reg[dr#1]->alur
		reg[dr#0] ^ alur->reg[dr#0], prefetch
		
mov		mem[pc]->cu, pc++
		nop
		reg[dr#1]->reg[dr#0], prefetch
		
cmp		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] - alur (Set flags accordingly), prefetch
		
add		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] + alur->reg[dr#1], prefetch
		
adc		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] + alur + C->reg[dr#1], prefetch
		
sub		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] - alur->reg[dr#1], prefetch
		
sbc		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] - alur - C->reg[dr#1], prefetch
		
and		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] & alur->reg[dr#1], prefetch
		
or		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] | alur->reg[dr#1], prefetch
		
////MULT option #1
//mult	mem[pc]->cu, pc++
//		reg[dr#1]->alur, prefetch
//		(reg[dr#0] * alur) & 0x0000FFFF->reg[0], prefetch
//		(reg[dr#0] * alur)>>16->reg[1], prefetch
		
//MULT option #2
mult	mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		(reg[dr#0] * alur) & 0x0000FFFF->reg[0], (reg[dr#0] * alur)>>16->reg[1], prefetch
		
////DIV option #1
//div		mem[pc]->cu, pc++
//		reg[dr#1]->alur, prefetch
//		reg[dr#0] % alur->reg[0], prefetch
//		reg[dr#0] / alur->reg[1], prefetch
		
//DIV option #2
div		mem[pc]->cu, pc++
		reg[dr#1]->alur, prefetch
		reg[dr#0] % alur->reg[0], reg[dr#0] / alur->reg[1], prefetch
		
ibr.	mem[pc]->cu, pc++
		if (rcc matches fr) reg[ar + 56]->pc
		
br.		mem[pc]->cu, pc++
		if (cc matches fr) mem[pc]->pc
		
rbr.	mem[pc]->cu, pc++
		if (cc matches fr) pc + mem[pc]->pc
	
	
interrupt
		iv->pc

exception
		mem[pc]->cu, pc++		//The processor is not currently aware that the instruction is bad.
		0x0002->pc, pc - 1->iv	//Now it knows and the processor takes action.