Overview:
| CPU | 8BP2 |
| Data | 8 bits |
| Memory | 16 bits |
| Architecture | Von Neumann |
| Technology | TTL and Verlog |
| Estimated chip count | 52 |
| Status | Designed; Never built in TTL, and Verilog version does not seem to work |
| Successor | 8BP3 |
| Time period | September 2015 - July 2016 |
Problems:
- Doesn't work
- Uses transparent latchs, which may be why it did not work in simulation
- Arrays are impossible without self-modifying code
Immediately after I finished my first CPU, I wanted to make another one to fix the flaws in 8BC, the most important of which was the tiny memory. 256 B is only enough room for about 80 instructions, but 64 kB is enough to turn it into a real microcomputer. I was not content with the lack of instructions and the missing subroutine stack, so of course I had to feed my obsession and start yet another CPU project.
Instruction Set:
| Opcode | Mnemonic | Operands | Function |
|---|---|---|---|
| 0 | ALU1 | A, B, C or A, B | ALU operation where Cn in is 1. f(A, B) → C or f(A) → B. Two or three operands depending upon the operation chosen. |
| 1 | ALU0 | A, B, C or A, B | ALU operation where Cn in is 0. f(A, B) → C or f(A) → B. Two or three operands depending upon the operation chosen. |
| 2 | TC | A, B | Compare memory[A] and memory[B]. Set condition codes. |
| 3 | LPC | Latch program counter (PC) into registers external to the CPU. See the documentation for more details. | |
| 4 | IN | A, B | Read from I/O port A and store in memory[B]. |
| 5 | OUT | A, B | Read from memory[B] and write to I/O port A. |
| 6 | RET | Return from interrupt. | |
| 7 | JC | CC, JH, JL | If the selected condition is met, then jump to {memory[JH], memory[JL]}. |
First instruction word:
| 3'opcode | ALU M | 4'ALU select |
The ALU control signals are directly connected to a 74181 ALU. The chip datasheet is required for programming this computer.
All operands are two bytes that follows the first word in the order specified.
It is interesting writing this and noting the close similarities between 8BC and 8BC2. It is also interesting that even with those similarities, 8BC2 took many months longer than 8BC to complete. 8BC was finished in about 2 weeks.
Files:
8BP2 Documentation (pdf)8BP2 Instruction Set (pdf)
8BP2 Programs (pdf)
8BC2 Verilog Sources (zip)
8BC2 out-of-date schematics (zip)