Overview:
| CPU | 4BP |
| Data | 4 bits |
| Memory | 16 bits |
| Registers | 256 |
| Architecture | Von Neumann |
| Technology | Verlog on FPGA |
| Status | Only a few instructions implemented |
| Successor | None |
| Time period | July 2016 |
Problems:
- Perfect in every way
The truth is that 4BP was never meant to be a serious and fully functional computer, so when I killed it, I forgave all of its sins and imperfections. It was merely an experiment in addressing modes. This is actually one of the few cases that a 4-bit architecture is an advantage because the goal was partially to find a faster way of addressing large amounts of memory with a small bus width.
With a 4-bit computer, you might expect the first nybble to contain the opcode and the following nybbles to contain the addresses of the operands. This is correct with one modification. The second nybble specifies the addressing mode of the first and second operands. Looking at the instruction set right now, it does not look completely regular, so like 8BP3, it may be time consuming to implement all of the addressing modes. The most important addressing modes were the small, medium, large, and very-large addressing. As you could probably guess, these correspond to 4, 8, 12, and 16 bit addressing. This provides multiple tiers of addressing speed, sort of like the 6502's 256 "registers" in memory.
The most important part of this project was not the investigation into addressing modes, but that 4BP executed its first instruction in simulation on 8/17/2016. Up to this point, I had been unsuccessful in goading my CPUs to run.
Files:
4BP Verilog source(zip)